How can I design VHDL modal in the following details?

Design VHDL model of a functional unit called sign-extender unit used in some processors. Input of this unit is 4-bit signed binary number and output is 8 bit signed binary number. The unit preserves magnitude and sign of the number.

Here is my code and it doesn't work. I'm beginner. Please help and explain. Many thanks.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sign_extender is
    port
    (   
        a: in std_logic_vector (3 downto 0);
        q: out std_logic_vector (7 downto 0);
    );
end sign_extender;

architecture sign_extender_arch of sign_extender is
begin -- architecture
    q <= a;
end sign_extender_arch;